There is a recent discussion atHi,
I have tested speed (in sipmle loop, C++, 10MHz clock) of SPI bus, but speed of Raspberry Pi 5 is much worse than 4B.
The clock in the SPI data burst is the same, but time lag between bursts is approx. 10x longer @ Pi 5 than @ 4B.
I suppose it is because of different HW, but the fast SPI is unusable now...
Can you help / explain me this? Thank you
https://forums.raspberrypi.com/viewtopi ... 8#p2226128
concerning added PCIe latency in the Pi 5 design versus available bandwidth. I don't know what can be done for your application, but you may want to post a note with a link here to attract the attention of the experts in that other thread.
Unfortunately the private messaging system has been disabled to comply with European law.
Statistics: Posted by ejolson — Tue Jun 04, 2024 4:03 am