I have not seen anything which indicates the possibility of controlling the gate time period. It takes 96 clock cycles to determine an ADC result, and I guess some number of those make for the gate time period. Lowering the clock rate would presumably increase the gate time period. However that clock is meant to be 48 MHz according to the datasheet so I don't know what consequences there would be in lowering it.
The other alternative is simply to do multiple reads which effectively extends the gate time period.
That would be my recommendation anyway as it avoids the problem of the S&H cap creeping upwards when not read for a while, making some readings way too high - viewtopic.php?t=354874
There is nothing in the datasheet I could see which indicates what the gate sample time is. Given it's an SAR conversion it could be that the gate time is the full 96 cycles, with the error flags intended to be used to detect when the voltage no longer matches what the reading suggests.
The other alternative is simply to do multiple reads which effectively extends the gate time period.
That would be my recommendation anyway as it avoids the problem of the S&H cap creeping upwards when not read for a while, making some readings way too high - viewtopic.php?t=354874
There is nothing in the datasheet I could see which indicates what the gate sample time is. Given it's an SAR conversion it could be that the gate time is the full 96 cycles, with the error flags intended to be used to detect when the voltage no longer matches what the reading suggests.
Statistics: Posted by hippy — Wed Jul 17, 2024 2:18 pm