General • Re: PIO+DMA w/ offset?

thank you both for your quick responses!

IN Y, 16# Left shift 16 high bits from Y register into ISR

i hadn't considered that i can get an offset via the scratch registers being shifted in - that's a neat idea

I think it could work through DMA chaining with PIO, not sure

i'm actually not sure it will be fast enough either i think it takes 22 cycles for random flash access which, if it's overclocked, should leave me with enough time for most of the hosts. an experiment nonetheless

Statistics: Posted by zenzizen — Mon Sep 30, 2024 2:01 am

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