I have no idea what that tool interface is.
From the LTSSM trace, I deduce that
- Your FPGA did not present RX terminations for at least 71ms after PERST# was released
- Thereafter, it presented RX terminations but the RC didn't detect TX activity, so the RC assumed it was connected to a test fixture and autonomously entered compliance mode.
- The driver gave up waiting after 250ms and reasserted PERST#
What drives the link state machine of the FPGA endpoint?
From the LTSSM trace, I deduce that
- Your FPGA did not present RX terminations for at least 71ms after PERST# was released
- Thereafter, it presented RX terminations but the RC didn't detect TX activity, so the RC assumed it was connected to a test fixture and autonomously entered compliance mode.
- The driver gave up waiting after 250ms and reasserted PERST#
What drives the link state machine of the FPGA endpoint?
Statistics: Posted by jdb — Mon Sep 01, 2025 8:14 pm