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Interfacing (DSI, CSI, I2C, etc.) • Re: RP1 PIO issues with FIFO or DMA underflow

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It's a bug/deficiency in the kernel PIO driver, awakened by the fairly recent change to increase the DMA burst size. The RX FIFO DMA threshold level is being set to 1, even though the burst size is 4 (unless DMA channels 0 & 1 are busy), which can lead to underflow as you've seen. I thought there would be a simple workaround (an explicit call to pio_sm_set_dmactrl), but it's not cooperating.

Statistics: Posted by PhilE — Wed Jan 07, 2026 5:30 pm



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