I have an interest in building a backplane for 8 RP2350 boards sort of like a PLC or data acquisition system. This is a hobby project. I don't have any experience in making a backplane. I did some research on what I think I need and how I want it to work. I originally looked at the Revolution Pi controller with their I/O cards. They are using a relative slow RS485 interface for the I/O. I also looked at the Beckhoff EK1100 type of EtherCAT couplers with their EBus backplane. That seems more like what I'm interested in and the kind of data transfer rates I'm looking for.
I have been playing around with a W6300 Pi Pico 2 device. I've been getting very low latency and jitter using UDP. I figured that would be my PC connection to the backplane. Because the Pi Pico has the PIO controllers I figured I could do something like an EtherCAT frame stuffing routine using a pipelined transmit and recieve through the RP2350s. Based on what I can tell about the Beckhoff EBus its an LVDS system and it doesn't have that many pins so I'm assuming it's got a clock, recieve and transmit going from device to device with some power lines or some other comms bus in there.
I found a quad LVDS with 2 transmitters and 2 recievers from TI with part number SN65LVDS049PWR. The device is rated for 400Mbit so it's more than good enough for a 150Mhz Pico. I'm thinking of putting two of these on each RP2350 board for testing and wiring 4 transmitters and 4 recievers into the PIO. I think I only need 3 of them for each board to board connection. I was going to attempt to run the data transfer between 20 and 50Mbit. Which seems doable on the RP2350.
My goal is to have a custom controller with a 1kHz loop rate so I want the bus speed to be fast enough to not eat up all of my 1000ms loop time. I figured if each module is given a fixed 64 bytes of I/O (32 in and 32 out) plus another 20 bytes of data/CRC I should be able to transfer 8 slots back to the master in about 200us.
I haven't really experimented with the PIO or the LVDS chips yet so I was looking for some feedback if it sounds like a reasonable project for the RP2350. I've seen PIO projects that implement SPI and this isn't much different from that other than each node would need to count clocks to figure out where their data is in the jumbo frame. I'm going to order some of the LVDS chips anyway and start messing around with them. To test this I'm going to just wire some CAT5 cables between the boards since the data sheet says it's designed for cables / backplanes with an impedance of 100ohm. Any suggestions or other ideas of how to tackle this would be appreciated.
I have been playing around with a W6300 Pi Pico 2 device. I've been getting very low latency and jitter using UDP. I figured that would be my PC connection to the backplane. Because the Pi Pico has the PIO controllers I figured I could do something like an EtherCAT frame stuffing routine using a pipelined transmit and recieve through the RP2350s. Based on what I can tell about the Beckhoff EBus its an LVDS system and it doesn't have that many pins so I'm assuming it's got a clock, recieve and transmit going from device to device with some power lines or some other comms bus in there.
I found a quad LVDS with 2 transmitters and 2 recievers from TI with part number SN65LVDS049PWR. The device is rated for 400Mbit so it's more than good enough for a 150Mhz Pico. I'm thinking of putting two of these on each RP2350 board for testing and wiring 4 transmitters and 4 recievers into the PIO. I think I only need 3 of them for each board to board connection. I was going to attempt to run the data transfer between 20 and 50Mbit. Which seems doable on the RP2350.
My goal is to have a custom controller with a 1kHz loop rate so I want the bus speed to be fast enough to not eat up all of my 1000ms loop time. I figured if each module is given a fixed 64 bytes of I/O (32 in and 32 out) plus another 20 bytes of data/CRC I should be able to transfer 8 slots back to the master in about 200us.
I haven't really experimented with the PIO or the LVDS chips yet so I was looking for some feedback if it sounds like a reasonable project for the RP2350. I've seen PIO projects that implement SPI and this isn't much different from that other than each node would need to count clocks to figure out where their data is in the jumbo frame. I'm going to order some of the LVDS chips anyway and start messing around with them. To test this I'm going to just wire some CAT5 cables between the boards since the data sheet says it's designed for cables / backplanes with an impedance of 100ohm. Any suggestions or other ideas of how to tackle this would be appreciated.
Statistics: Posted by theoutfield — Thu Jan 08, 2026 3:03 am