HATs and other add-ons • Pi 5 PCIe PWR_EN vs RST timing

Can anyone tell me whether the Pi 5 observes the PCIe standard specification for timing of the RST signal versus power rails? The specification says that there must be a minimum 100ms delay between power rails of a device becoming stable and reset going inactive (i.e. high).

As I understand it, the PWR_EN signal on the PCIe connector is used to signal to a HAT that power supplies should be powered up. Presumably this is toggled only if a device is detected at boot (by the state of the DET_WAKE pin), and also according to changes of the Pi's power state (e.g. ACTIVE, STANDBY, etc). So, ideally there should be this delay between PWR_EN and RST. Does the Pi 5 do this?

I ask because on a HAT I'm designing I am using PWR_EN to switch the enable inputs of a couple of voltage regulators (3.3V and 1.2V) that power the PCIe device. It wouldn't be helpful if the Pi 5 de-asserts RST simultaneously with (or very soon after) PWR_EN being toggled - I don't think the device wouldn't get its required initialisation time. If so I'd need some kind of voltage supervisor to gate the RST signal and enforce the necessary delay. But obviously, it'd be preferable if I didn't need this.

Statistics: Posted by HwAoRrDk — Sun Mar 10, 2024 5:24 pm

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