The Cortex-M0+ is not recommended for this. Higher RSA bit counts will significantly decrease performance. I remember messing around on PIC32MX with SSL. The CPU gets loaded hard and you have to manage this. (Reserve a core.) The problem that occurs is you risk socket timeout. With web browser this would be very annoying.
Moving over to a Pi would be better for this. Honestly L4-L6 networking is out of the class of M0+. M3 is capable of some L2-L4. Crypto processors are likely capable of working around this but these are usually hard to integrate.
2048 bit may not be recommended much and when they require 4096 bit, TLS basically requires Cortex-A with Linux. Granted this assumes you need decent bandwidth. You still need something like AES-256 which may require coprocessor.
My guess is this is on XIP which is why the performance drop is so low compared to PIC32MX.
Moving over to a Pi would be better for this. Honestly L4-L6 networking is out of the class of M0+. M3 is capable of some L2-L4. Crypto processors are likely capable of working around this but these are usually hard to integrate.
2048 bit may not be recommended much and when they require 4096 bit, TLS basically requires Cortex-A with Linux. Granted this assumes you need decent bandwidth. You still need something like AES-256 which may require coprocessor.
My guess is this is on XIP which is why the performance drop is so low compared to PIC32MX.
Statistics: Posted by dthacher — Mon Jan 22, 2024 5:03 am